Logical elements and diagrams

Содержание и основные понятия

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Alterna · Chapter 16 · page 16.3
Logical elements and diagrams
AND, OR, NOT, NAND, NOR, XOR. SVG diagrams + designer + decryptor/multiplexor.
The logic valve is the physical execution of the logic operation (transistor scheme). Billions of valves form a processor. Each computer is a giant composition of the AND, OR, NOT.
GEF
PIF
OGE No. 3
01
Main valves (SVG)
AND (∧)
A
B
A∧B
OR (∨)
A
B
A∨B
NOT (¬)
A
¬A
NAND
¬(A∧B)
AND + NOT. Universal element: Through NAND, everyone else can be expressed.
NOR
¬(A∨B)
XOR (⊕)
A⊕B
02
Schematic simulator
Scream through the entrances - see the way out
🔌
Schematic: (A)B(BA\B) is XNOR (equivalent)
A=0
B=0
∧
A∧B
∧
¬A∧¬B
∨
0
F = (A∧B)∨(¬A∧¬B) = A↔B (XNOR). Эта схема выдаёт 1, когда A и B равны.
03
Logical equations
Find a set of variables where the formula is true
What is the logical equation?
Logic equation
- is a logical formula that needs to find a set of variables that make the formula true (F = 1). The solution is all lines of the truth table where the result is 1.
Example: decide equation A ~ B = 1
The situation is equal to 1 only when both operands are equal to one.
A=1, B=1
.
Example: decide equation A B = 1
XOR gives 1 at different values. Decisions:
(A=0,B=1)
and
(A=1,B=0)
.
For EGE No. 15
Logical equations are the standard task of the EGE No. 15: Algorithm: build a table of truth, find all the lines with F=1.
🧮
Logic equations solver
Enter the equation (formula = 1) — get all the solutions
Equation F = 1
04
Why NAND is Universal
You can build any logical operation through NAND.
NAND universality (Strich Schaeffer)
NAND
- The only valve you can get everyone else from:
NOT
: ¬A = A NAND A
AND
: A∧B = (A NAND B) NAND (A NAND B)
OR
: A∨B = (A NAND A) NAND (B NAND B)
🔬
Evidence: NAND ♪ NOT, AND, OR
NOT via NAND
¬A = A NAND A
NAND
¬A
A
A
Both entrances are connected by the NAND(A,A) = B(A)=BA
AND via NAND
A∧B = (A NAND B) NAND (A NAND B)
A
B
NAND
X
X
NAND
A∧B
X = A NAND B, then X NAND X = BX =
OR via NAND
A∨B = (A NAND A) NAND (B NAND B)
A
NAND
¬A
B
NAND
¬B
NAND
A∨B
BA NAND BB = B(ABA: BB) = A\B (the law of Morgan)
Fact
All processors are built from NAND (or NOR) because it is cheaper and easier to manufacture than individual AND/OR/NOTs.
05
Schematic Designer
Pull the elements to the canvas -- collect the diagram -- get the truth table.
How to Collect a Scheme
1.
Pick an element
In a palette on the left, and press it, it will appear on the canvas.
2.
Move.
elements by dragging (drag) through the canvas.
3.
Connect the elements:
click on
exit
(right circle) element, then click on
Incoming
(left circle) the other one - the wire will appear.
4. Press
"Check"
- get the truth table for the whole scheme.
🔧
Drag-and-drop circuit designer
Push the element in the palette, drag it to the canvas, connect the exit.
:: Elements palette:
06
Discrypter and Multilexor
Key combining schemes for the EEG/EGE
Decoder
Decipher
- Scheme with n entrances and 2
n
Only the exit that matches the binary code at the entrances is activated.
For 2 entrances (A, B) to 4 exits (Y0 - Y3):
A
B
Y0
Y1
Y2
Y3
0
0
1
0
0
0
0
1
0
1
0
0
1
0
0
0
1
0
1
1
0
0
0
1
Formulas
Y0 = ¬A∧¬B   Y1 = ¬A∧B   Y2 = A∧¬B   Y3 = A∧B
📡
Decryptor 2~4: Interactor
A=0
B=0
2→4
Decoder
Y0=0
Y1=0
Y2=0
Y3=0
Y0
Y1
Y2
Y3
Multiplexor (MUX)
Multilexor
- "data switch." Chooses one of the 2
n
and transmits it to the only exit. n inlet controller + 2
n
Data entry = 1 exit.
For 4-channel MUX (2 controls: S0, S1):
S1
S0
Y
0
0
D0
0
1
D1
1
0
D2
1
1
D3
Formula
Y = (¬S1∧¬S0∧D0) ∨ (¬S1∧S0∧D1) ∨ (S1∧¬S0∧D2) ∨ (S1∧S0∧D3)
🔀
Multilexor 4x1: Interactor
Data:
D0=1
D1=0
D2=1
D3=0
00
01
10
11
MUX 4:1
4→1
S0=0
S1=0
Management
1
Channel D0 selected