Digital electronics

Содержание и основные понятия

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Alterna · Chapter 16 · page 16.2
Digital electronics
Semi-summer, RS-trigger, full summer, D-trigger, counter.
Digital electronics is a world where billions of transistors work according to the laws of mathematical logic, and here we see the basic digital elements: computors, triggers and counters.
GEF
PIF
OGE
EEG
§01
Semi-summer
What's a semi-summer?
Semi-summer
The result is two exits:
S
(amount) and
C
(carriage)
A
B
S (amount)
C (transfer)
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
Formulas
S = A ⊕ B
(Amount - XOR)
C = A ∧ B
(carriage - AND)
🧮
Interactive Semi-summer
A=0
B=0
⊕
S = 0
∧
C = 0
Entry A
Entry B
Amount (XOR)
Transfer (AND)
0 + 0 = 0 (no transfer)
§02
RS-trigger
What's RS-trigger?
RS-trigger
It has two entrances:
R
(Reset dumping) and
S
Set - Installation and Exit
Q
.
S
R
Q (previous)
Q (below)
Action
0
0
0
0
Memories
0
0
1
1
Memories
1
0
—
1
Installation (set)
0
1
—
0
Reset
1
1
—
?
Forbidden!
💾
RS Trigger: Simulator
Press S and R — Monitor Q Status
S=0
R=0
RS-TRIGGER
0
Q
0
Set
Reset
Q = 0 ♪ Memories
§03
Full Computator
From semi-summer to full
Full Computator
(Full Adder) builds up three bits: A, B and
Cin
(incoming transfer) is built from two semi-summers + OR.
A
B
Cin
S (amount)
Cout (transfer)
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
Formulas
S = A ⊕ B ⊕ Cin
Cout = (A∧B) ∨ (A∧Cin) ∨ (B∧Cin)
📐
Total summator scheme
two semi-summers + OR
A
B
Cᵢₙ
Semi-summer 1
XOR
AND
S₁
C₁
Semi-summer 2
XOR
AND
C₂
C₁
C₂
OR
S = 0
Cₒᵤₜ = 0
Amount
transport
➕
Total sum: 3 entries ~ sum + carry-over
S (amount)
0
+
Cout (transfer)
0
0 + 0 + zero = 0 (transfer: 0)
§04
D-trigger
D-trigger (Data flip-flop)
D-trigger
It memorizes the value at inlet D.
Only when the CLK tactical signal is increasing
(rising edge) Unlike RS Trigger, he only has one entry -- no prohibited state.
The D-trigger is built from RS-trigger + inverter: the D signal comes to S and the VD comes to R. When CLK=1, RS-triger "receives" the value D. When the CLC=0 is memorized.
Where applicable:
Processor registers, memory buffers, simultaneous machines. A modern processor contains billions of D-triggers, one for each bit of the register.
CLK
D
Q (below)
Action
0→0
—
Q (previous)
Memories
0→1
0
0
Recording D=0
0→1
1
1
Recording D=1
1→0
—
Q (previous)
Memories
💾
D-trigger: diagram and simulator
Set D, then press CLK (rising edge) – Q will remember D
D=0
CLK
RS-TRIGGER
S
R
0
CLK
Q = 0
Data
Tact
Withdrawal
Q = 0 x CLK expected
§05
The meter
D-trigger counter
The meter
The basic logic that counts the impulses of the CLK tactical signal and produces the result in a binary form. The simplest 2-bit counter counts 0 to 3:
00₂ → 01₂ → 10₂ → 11₂ → 00₂
(cyclically).
How it works:
Two D-triggers are connected in sequence. The Junior Trigger (FF0) is switched to each CLK. The Senior Trigger(FF1) is switched when the Junior moves from 1 to 0 (i.e. "overfilling").
Where applicable:
Pulse counters, target memory tyres, frequency dividers, timers. Every ticking signal from the processor passes through the meter chain.
🔢
2-bit meter: diagram and simulator
CLK ↑
FF0 (beat 0)
0
Q0
0
FF1 (beat 1)
0
Q1
0
Bit0
Bit1
00
=
0
/ 3
The counter: 0 steps: 0