Transistor schemes

Содержание и основные понятия

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Alterna · Chapter 16 · page 16.1
Transistor schemes
Transistor as a key, NOT from transistors, semi-summer, multiplier, TTL, NAND.
§01
Transistor as Key
Transistor
- A semiconductor device that works as an electrical key. By controlling the pressure on the shut-off (gate), we lock or unlock the circuit between the runoff (drain) and the source (source).
NMOS:
at "1" on the shut-off, closes the chain (source of the source).
PMOS:
at "0" on the shut-off, closes the circuit.
CMOS Complementary pair
===Intel Core i9: ~4 billion, Apple M2: ~20 billion)===The Intel Core I9 (NMOS + PMOS) is the foundation of all modern chips.
Try it.
Press the "A" button or the NMOS rectangle to turn the lamp on or off.
⚡
Transistor as a switch
NMOS control lamp
VCC (+5V)
OFF
NMOS
D
GND
A = 0
A = 0 ♪ NMOS ♪ lamp closed ♪
§02
NOT of transistors: Inverter
Invertor (NOT)
The diagram is: +5V x resistor R x NMOS ~ GND. The output is between R and NMOs.
A=0 × NMOS kicked R "pulls" the exit to +5V ~ Y=1. A=1 ~ NMOs closed ~ R "tracts" the release to GND ~ y=0.
Formula:
Y = ¬A
Try it.
Press the NMOS shutter or the "A" button - watch the exit invert.
🔄
NMOS inverter
Y = ¬A
+5V
R
Y = 1
NMOS
GND
A=0
exit
A = 0 ♪ NMOS ♪ R pulls to +5V ♪ Y=1 ♪
§03
Semi-summer: addition of two bits
Semi-summer
Computes two binary numbers A and B. Result:
S
(amount) and
C
(carriage)
S = A ⊕ B (XOR),  C = A ∧ B (AND).
A
B
S (amount)
C (transfer)
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
Application: Semiconductor Calculators, ALU (Arifmetics) Processor.
Try it.
Press A or B, the diagram will show the sum of S and the real-time transfer of C.
➕
Semi-summer
S = A ⊕ B, C = A ∧ B
A = 0
B = 0
XOR
AND
S = 0
C = 0
Amount
transport
0 + 0 = 0 (no transfer)
§04
Multiplicator: shift and addition
Multiplier
It's made up of semi-summers and full codators. The algorithm: "shift-and-add" is the same as we do on paper.
Example: 3 × 2 in binary:
11 × 10 = 110 (6).
Step
Operation
Result
1
11 × B₀(=0)
00
2
11 × B1(=1), shift "1"
110
3
Amount
00 + 110 = 110 = 6₁₀
Scheme
Two-bit multiplier: 4 AND-ventil for partial production + half-summer for addition.
📐
Scheme of a two-bit multiplier
A₁A₀ × B₁B₀ → P₃P₂P₁P₀
Entry A
A₀
A₁
Entry B
B₀
B₁
AND
P₀
AND
AND
AND
Semi-summer
← from AND2,AND3
P₁
Semi-summer
P₂
P₃
bt 0 (Associate)
Bit 1
Bits 2
bat 3 (senior)
Try it.
Select the 2-bit numbers A and B with buttons; the multiplier will show the step algorithm "swipe and addition".
✖️
Two-bit multiplier
Algorithm "switch and addition"
Number A (Junior Bit - Senior)
A = 0
Number B (Junior bit ♪ Senior)
B = 0
Result: 0
§05
TTL: Bipolar transistors logic
TTL (Transistor-Transistor Logic)
==History==The BJT family is the base of the first microscheme (74xx series).
by current
Bases, not shut-off voltage like MOSFET.
TTL Basic Rules
Parameter
Meaning
LOW (log 0)
0 B - 0.8 V
HIGH (log 1)
2.0 B - 5.0 V
Prohibited zone
0.8 B - 2.0 V (no signal defined)
Fan-out
One exit loades to
10
entrances
Delay
~10 ns per valve
Nutrition
+5 V, ~10 MW per valve
Digital circuit(s):
Duplicity:
The signal only takes two values, 0 or 1.
Unidentity:
For each set of entrances, there is an exit.
Stability:
At fixed entrances, the exit shall be stabilized over time.
Compositionality:
from the basic elements (AND, OR, NOT) you can build any boolean function.
Comparison
TTL vs CMOS:
TTL is faster but consumes more energy.
§06
NAND from transistors
NAND (NE-I)
- Universal logical element: any other valve (AND, OR, NOT, NOOR, XOR...) can be built from one NAND.
Formula:
Y = B(A ~ B). Exit = 0 only when both entrances are equal to 1.
A
B
A ∧ B
Y = ¬(A ∧ B)
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
CMOS implementation:
2 PMOS parallel (to VDD) + 2 NMOS sequenced (to GND). Output = 1 while at least one NMOSS is off.
Try it.
Press A or B - watch the transistors switch and control the exit.
NAND
NAND from CMOS transistors
Y = ¬(A ∧ B)
VDD (+5V)
PMOS A
PMOS B
Y = 1
NMOS A
NMOS B
GND
A=0
B=0
parallel
consecutively
A = 0, B = 0 ~ at least 1 PMOS in, NMOS unopened ~ Y = 1